1. Field
The present invention relates to a ferroelectric memory device.
2. Description of the Related Art
Next-generation nonvolatile memories are being developed which have features that rewriting can be performed faster and the maximum allowable number of rewrite operations is five order or more larger than in the conventional EPROM and flash memory and which are comparable to the DRAM in capacity, operation speed, and cost. Such next-generation nonvolatile memories include an FeRAM (ferroelectric random access memory), an MRAM (magnetic random access memory), a PRAM (phase change random access memory) and an ReRAM (resistive random access memory). In the FeRAM which is a ferroelectric memory, memory cell tests such as a 0-write/0-read test and a 1-write/1-read test are performed by changing the reference potential (refer to JP-A-2002-216498, for example).
FeRAM test methods described in JP-A-2002-216498 etc. include a method in which reference potentials are applied directly to bit lines from outside the chip and a method in which reference potentials are applied to bit lines using reference potential generation circuits which incorporate a capacitor. The method in which reference potentials are applied directly from outside the chip has a disadvantage that it takes long time to precharge bit lines. The method using the reference potential generation circuits has a disadvantage that it takes long time to switch the reference potential.